Description of Invention
This project integrates the NEORV32 RISC-V processor onto an FPGA, showcasing the open-source ISA's flexibility. The NEORV32 core was chosen for its configurability and peripheral support, including UART and GPIO. The process involved setting up the development environment, synthesizing the core and verifying functionality. The integration was demonstrated with a holonomic X-drive mobile robot, handling tasks like quadrature encoding, inverse kinematics, and PID control, validating the processor's capability which highlights the practicality of RISC-V on FPGAs.